? semiconductor components industries, llc, 2005 october, 2005? rev. 11 1 publication order number: mc100lve222/d mc100lve222 3.3 v/5.0 vecl 1:15 differential 1/ 2 clock driver the mc100lve222 is a low skew 1:15 differential 1/ 2 ecl fanout buffer designed with clock distribution in mind. the lvecl/lvpecl input signal pairs can be differential or used single?ended (with v bb output reference bypassed and connected to the unused input of a pair). either of two fully differential clock inputs may be selected. each of the four output ba nks of 2, 3, 4, and 6 differential pairs may be indwependently configured to fanout 1x or 1/2x of the input frequency. the lve222 speci fically guarantees low output to output skew. optimal design, layout, and processing minimize skew within a device and from lot to lot. the fsel pins and clk_sel pin are asynchronous control inputs. any changes may cause indeterminate out put states requiring an mr pulse to resynchronize any 1/2x outputs. the device tpd is affected by the quantity of output pairs terminated with a minimum occurring with only one output pair and increasing about 10?20 ps for all output pairs. relative skew distribution is not affected as more pairs are terminate d, but the increased tpd does shift the entire distribution. unused output pairs should be left unterminated (open) to reduce power and switching noise. the mc100lve222, as with most ecl devices, can be operated from a positive v cc /v cco supply in pecl mode. this allows the lve222 to be used for high perform ance clock distribution in +3.3 v systems. opera tion with >3.8 | (v cc or v cco ?v ee | span will require special thermal handling considerations. designe rs can take advantage of the lve222?s performance to distribute low skew clocks across the backplane or the board. in a pecl e nvironment series or thevenin line, terminations are typically used as they require no additional power supplies. all power supply pins must be connected. for more information on using pecl, designers should refer to application note an1406/d. for a spice model, refer to application note an1560/d. ? 200 ps part?to?part skew ? 50 ps output?to?output skew ? selectable 1x or 1/2x frequency outputs ? esd protection: >2 kv hbm, >200 v mm ? the 100 series contains temperature compensation ? pecl mode operating range: v cc /v cco = 3.0 v to 5.25 v with v ee = 0 v ? necl mode operating range: v cc /v cco = 0 v with v ee = ?3.0 v to ?5.25 v ? internal input pulldown resistors ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 2 for additional information, refer to application note and8003/d ? flammability rating: ul 94 v?0 @ 0.125 in, oxygen index: 28 to 34 ? transistor count = 684 devices ? pb?free packages are available* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. lqfp fa suffix case 848d marking diagram* *for additional information, see application note and8002/d 1 52 a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package mc100lve awlyywwg 222 http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information
mc100lve222 http://onsemi.com 2 vcco vcc o qc0 qc0 qc1 qc1 qc2 qc2 qc3 qc3 vcc o nc nc vcc o vcc mr fsela fselb clk0 clk0 clk_sel clk1 clk1 vbb fselc fseld vee 40 41 42 43 44 45 46 47 48 49 50 51 52 25 24 23 22 21 20 19 18 17 16 15 14 12345678910111213 39 38 37 36 35 34 33 32 31 30 29 28 27 26 qd5 qd5 qd4 qd4 qd3 qd3 qd2 qd2 qd1 qd1 qd0 qd0 vcco qa0 qa0 qa1 qa1 vcco qb0 qb0 qb1 qb1 qb2 qb2 vcco qa0:1 clk0 mr 2 2 1 fsela clk0 clk1 clk1 clk_sel qa0:1 qb0:2 3 qb0:2 v bb fselb qc0:3 4 qc0:3 fselc qd0:5 6 qd0:5 fseld mc100lve222 figure 1. pinout assignment (top view) note: all v cc /v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. all v cc /v cco pins are internally interconnected. table 1. pin description function ecl differential input clock ecl differential input clock ecl clock select ecl master reset ecl differential outputs ecl differential outputs ecl differential outputs ecl differential outputs ecl 1 or 2 select reference voltage output positive supply (v cc = v cco ) negative supply no connect pin clk0, clk0 clk1, clk1 clk_sel mr qa0:1, qa0:1 qb0:2, qb0:2 qc0:3, qc0:3 qd0:5, qd0:5 fseln v bb v cc /v cco v ee nc figure 2. logic diagram table 2. function table input function active clk0 1 mr clk_sel fseln lh reset clk1 2
mc100lve222 http://onsemi.com 3 figure 3. timing diagram clk reset 1/2q q table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc /v cco pecl mode power supply v ee = 0 v 8 to 0 v v ee necl mode power supply v cc or v cco = 0 v ?8 to 0 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc or v cco = 0 v v i (v cc or v cco ) v i v ee 6 to 0 ?6 to 0 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 52 lqfp 52 lqfp 70 48 c/w c/w jc thermal resistance (junction to case) standard board 52 lqfp tbd c/w t sol wave solder <2 to 3 sec @ 248 c 265 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected.
mc100lve222 http://onsemi.com 4 table 4. lvpecl dc characteristics v cc or v cco = 3.3 v; v ee = 0.0 v (note 1) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee power supply current 122 136 122 136 125 139 ma v oh output high voltage (note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage (note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mv v ih input high voltage (single?ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single?ended) 1490 1825 1490 1825 1490 1825 mv v bb output voltage reference 1.92 2.04 1.92 2.04 1.92 2.04 v v ihcmr input high voltage common mode range (differential configuration) (note 6) vpp < 500 mv vpp 500 mv 1.3 1.6 2.9 2.9 1.2 1.5 2.9 2.9 1.2 1.5 2.9 2.9 v v i ih input high current 150 150 150 a i il input low current others clk0 , clk1 0.5 ?300 0.5 ?300 0.5 ?300 a a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. input and output parameters vary 1:1 with v cc /v cco . v ee can vary +0.3 v to ?1.95 v. operation with |v cc or v cco ?v ee | 3.8 v span will require special thermal handling considerations. 2. outputs are terminated through a 50 resistor to (v cc or v cco ) ? 2.0 v. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc /v cco . v ihcmr is defined as the range within which the v ih level may vary, with the device still meeting the propagation delay specification. the v il level must be such that the peak to peak voltage is less than 1.0 v and greater than or equal to v pp (min). table 5. lvnecl dc characteristics v cc or v cco = 0.0 v; v ee = ?3.3 v (note 4) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max i ee power supply current 122 136 122 136 125 139 ma v oh output high voltage (note 5) ?1085 ?1005 ?880 ?1025 ?955 ?880 ?1025 ?955 ?880 mv v ol output low voltage (note 5) ?1830 ?1695 ?1555 ?1810 ?1705 ?1620 ?1810 ?1705 ?1620 mv v ih input high voltage (single?ended) ?1165 ?880 ?1165 ?880 ?1165 ?880 mv v il input low voltage (single?ended) ?1810 ?1475 ?1810 ?1475 ?1810 ?1475 mv v bb output voltage reference ?1.38 ?1.26 ?1.38 ?1.26 ?1.38 ?1.26 v v ihcmr input high voltage common mode range (differential configuration) (note 6) vpp < 500 mv vpp 500 mv ?2.0 ?1.7 ?0.4 ?0.4 ?2.1 ?1.8 ?0.4 ?0.4 ?2.1 ?1.8 ?0.4 ?0.4 v v i ih input high current 150 150 150 a i il input low current others clk0 , clk1 0.5 ?300 0.5 ?300 0.5 ?300 a a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. input and output parameters vary 1:1 with v cc /v cco . v ee can vary +0.3 v to ?1.95 v. operation with |v cc or v cco ?v ee | 3.8 v span will require special thermal handling considerations. 5. outputs are terminated through a 50 resistor to (v cc or v cco ) ? 2.0 v. 6. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc /v cco . v ihcmr is defined as the range within which the v ih level may vary, with the device still meeting the propagation delay specification. the v il level must be such that the peak to peak voltage is less than 1.0 v and greater than or equal to v pp (min).
mc100lve222 http://onsemi.com 5 table 6. ac characteristics v cc or v cco = 3.3 v; v ee = 0.0 v or v cc /v cco = 0.0 v; v ee = ?3.3 v (note 7) symbo l characteristic ?40 c 25 c 70 c uni t min typ max min typ max min typ max f max maximum toggle frequency 1.2 > 1.5 1.2 > 1.5 1.2 > 1.5 ghz t plh t phl propagation delay to output in (differential) (note 8) in (single?ended) (note 9) mr 1040 940 1100 1140 1140 1250 1240 1290 1400 1080 980 1170 1180 1180 1320 1280 1330 1470 1120 1020 1220 1220 1220 1370 1320 1370 1520 ps t skew within?device skew (note 10) part?to?part skew (differential configuration) 50 200 50 200 50 200 ps tjitter random clock jitter (rms) < 1.0 < 1.0 < 1.0 ps v pp input swing (differential) (note 11) 400 1000 400 1000 400 1000 mv t r /t f output rise/fall time 20%?80% 200 600 200 600 200 600 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. v ee can vary +0.3 v to ?1.95 v. operation with |v cc or pv cco ?v ee | 3.8 v span will require special thermal handling considerations. 8. the differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 9. the single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the out put signal. 10. the within?device skew is defined as the worst case difference between any two similar delay paths within a single device. 11. v pp (min) is defined as the minimum input dif ferential voltage which will cause no increase in the propagation delay. the v pp (min) is ac limited for the lve222. a differential input as low as 50 mv will still produce full ecl levels at the output. figure 4. typical termination for output driver and device evaluation (refer to application note and8020 ? termination of ecl logic devices) driver device receiver device qd 50 50 v tt q d v tt = (v cc or v cco ) ? 2.0 v z = 50 z = 50
mc100lve222 http://onsemi.com 6 ordering information device package shipping ? mc100lve222fa lqfp?52 160 units / rail mc100lve222far2 lqfp?52 1500 / tape & reel MC100LVE222FAG lqfp?52 (pb?free) 160 units / rail mc100lve222far2g lqfp?52 (pb?free) 1500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1404 ? eclinps circuit performance at non?standard v ih levels an1405 ? ecl clock distribution techniques an1406 ? designing with pecl (ecl at +5.0 v) an1503 ? eclinps i/o spice modeling kit an1504 ? metastability and the eclinps family an1560 ? low voltage eclinps spice modeling kit an1568 ? interfacing between lvds and ecl an1596 ? eclinps lite translator elt family spice i/o model kit an1650 ? using wire?or ties in eclinps designs an1672 ? the ecl translator guide and8001 ? odd number counters design and8002 ? marking and date codes and8020 ? termination of ecl logic devices
mc100lve222 http://onsemi.com 7 package dimensions fa suffix lqfp package case 848d?03 issue d f ??? ??? clockwise c l ?x? x=l, m, n 1 13 14 26 27 39 40 52 4x 13 tips 4x n 0.20 (0.008) h l?m n 0.20 (0.008) t l?m seating plane c 0.10 (0.004) t 4x 3 4x 2 s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z s l?m m 0.13 (0.005) n s t plating base metal d j u b v b1 a s v1 a1 s1 ?l? ?n? ?m? ?h? ?t? 1 g 3x view y view aa 2x r r1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?l?, ?m? and ?n? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?t?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). dim a min max min max inches 10.00 bsc 0.394 bsc millimeters a1 5.00 bsc 0.197 bsc b 10.00 bsc 0.394 bsc b1 5.00 bsc 0.197 bsc c ??? 1.70 ??? 0.067 c1 0.05 0.20 0.002 0.008 c2 1.30 1.50 0.051 0.059 d 0.20 0.40 0.008 0.016 e 0.45 0.030 f 0.22 0.35 0.009 0.014 g 0.65 bsc 0.75 0.018 0.026 bsc j 0.07 0.20 0.003 0.008 k 0.50 ref 0.020 ref r1 0.08 0.20 0.003 0.008 s 12.00 bsc 0.472 bsc s1 6.00 bsc 0.236 bsc u 0.09 0.16 0.004 0.006 v 12.00 bsc 0.472 bsc v1 6.00 bsc 0.236 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref 1 3 2 07 12 07 0 0 ??? ??? ref 12 ref 12 ref 12 ref
mc100lve222 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mc100lve222/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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